Integrated circuit (IC) designs are sometimes referred to as intellectual property (IP) cores, or IP blocks or IPs. IPs are reusable designs that are sold or licensed by the designing party. Custom Analog, Custom Digital, and Mixed Signal IPs are typically schematic based and are usually hierarchical in organization. Hierarchical IP designs can also be based in a hardware description language (HDL) (e.g., Verilog, VHDL), or other text netlist (e.g., EDIF, SPICE, ITT/DEF, etc.). A top level or higher design level includes instances of various sub-blocks connected to each other. The hierarchical IPs include one or more sub-levels eventually leading to a leaf block that is included in a bottom most level. The sub-blocks and the leaf blocks can be composed of primitive components of a standard cell library or reference library, such as logic gates and transistors.
An important consideration in IC design is conserving power in the manufactured IC. A complex IP may use more than one supply voltage and may use more than one technique for power optimization. The sub-blocks and leaf blocks may use explicit power and ground pins that can be driven at a top level or can use connections inherited from other design levels (e.g., override-able connections).
A power intent specification for an electronic circuit design is typically in text form and the format of a power intent specification can be any well recognized power intent specification stand, such as the Common Power Format (CPP) and the Unified Power Format (UPF, e.g., both the Accellera UPF 0.0 and IEEE 1801 aka UPF2.0) standards for example.
A power intent specification for physically implemented IP designs allows programmable power connectivity (e.g., for reuse of the IP with different power supplies) and allows power experimentation with the IP, such as for low power management, low power simulation, IP integration, and form design verification for example. To enable integration of the IP into new designs, a power intent specification is needed so that the IN power connectivity can be checked in the context of the IPs instantiation into the designs.
Text editors are typically used in creating power intent specifications. The use of text editors in the creation of power intent specifications for an existing IP can be a tedious, time consuming and error pone task for a design engineer. The power intent is usually determined by a designer reverse-engineering the design by tracing the power connections and determining which of the sub-structures of the connected devices are controllers of the flow and consumption of power. As designs increase in size and complexity, so do the power intent specifications of the designs, and the probability of introducing errors into the power intent specification increases.
Further, in text-based editing, the user must manually keep track of the design object names that will be referenced in the power intent specification and enter all the power intent details correctly. The user also needs to keep track of edits made to the circuit design and manually update a previously created power intent specification to synchronize with the updated design. In addition, the text editor used to create the specification may not be able to provide feedback whether all the required design details are entered. If the resulting specification is syntactically as well as semantically clean but nevertheless contains design errors, special equivalence checking tools must be used to catch such errors. This equivalence checking adds cost and time to the design process.
The use of form-based applications to create power intent specifications for existing IP designs can provide some prompting to assist in entering all the correct details, but using these applications is still cumbersome for large designs and the likelihood of errors is still high. Most of the limitations associated with text editing arising out of a lack of direct coupling between the design editor and the power intent editor are also exist with respect to form based applications. For example, as in the text editor approach, the user must manually keep track of the design object names that will be referenced in the power intent specification and enter all the power intent details correctly. The user also needs to keep track of edits done to the design and manually update a previously created power intent specification to bring it in agreement with the design. The inventor has recognized a need for improved tools to help a design engineer create power intent specifications.